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K7B161835B 512kx36 & 1mx18 synchronous sram - 1 - rev. 3.0 april 2006 k7b163635b * samsung electronics reserves the right to c hange products or specification without notice. information in this document is provided in relation to samsung products, and is subject to change without notice. nothing in this document shall be construed as granting any license, express or implied, by estoppel or otherwise, to any intellectual property rights in samsung products or technology. all information in this document is provided on as "as is" basis without guarantee or warranty of any kind. 1. for updates or additional information about sams ung products, contact your nearest samsung office. 2. samsung products are not intended for use in life suppor t, critical care, medical, safety equipment, or simi- lar applications where product failure could result in lo ss of life or personal or ph ysical harm, or any military or defense application, or any governmental procuremen t to which special terms or provisions may apply. 18mb sync. burst sram specification 100tqfp with pb / pb-free (rohs compliant)
K7B161835B 512kx36 & 1mx18 synchronous sram - 2 - rev. 3.0 april 2006 k7b163635b document title 512kx36 & 1mx18-bit synchronous burst sram revision history rev. no. 0.0 0.1 0.2 0.3 0.4 1.0 2.0 3.0 remark advance preliminary preliminary preliminary preliminary final final final history 1. initial draft 1. update the dc current spec(i cc , i sb ) 1. change the isb,isb1,isb2 - isb ; from 120ma to 170ma - isb1 ; from 80ma to 150ma - isb2 ; from 80ma to 130ma 1. remove the 1.8v vdd voltage level 1. remove the -85 speed bin 1. finalize the datasheet 1. add the overshoot timing 1. change ordering information draft date mar. 23. 2004 may. 21. 2004 sep. 21. 2004 oct. 18. 2004 jan. 04. 2005 july 18. 2005 feb. 16. 2006 apr. 16. 2006
K7B161835B 512kx36 & 1mx18 synchronous sram - 3 - rev. 3.0 april 2006 k7b163635b 18mb sb sram ordering information note 1. p(q) [package type] : p-pb free, q-pb 2. c(i) [operating temperature] : c-commercial, i-industrial org. vdd (v) speed (ns) access time (ns) part number rohs avail. 1mx18 3.3/2.5 8.5 7.5 K7B161835B-p(q) 1 c(i) 2 75 512kx36 3.3/2.5 8.5 7.5 k7b163635b-p(q) 1 c(i) 2 75
K7B161835B 512kx36 & 1mx18 synchronous sram - 4 - rev. 3.0 april 2006 k7b163635b 512kx36 & 1mx18-bit sync hronous burst sram the k7b163635b and K7B161835B are 18,874,368-bit syn- chronous static random access memory designed for high performance second level cache of pentium and power pc based system. it is organized as 512k(1m) words of 36(18) bits and integrates address and control registers, a 2-bit burst address counter and added some new functions for high performance cache ram applications; gw , bw , lbo , zz. write cycles are internally self- timed and synchronous. full bus-width write is done by gw , and each byte write is per- formed by the combination of we x and bw when gw is high. and with cs 1 high, adsp is blocked to control signals. burst cycle can be initiated with either the address status pro- cessor(adsp ) or address status cache controller(adsc ) inputs. subsequent burst addresses are generated internally in the system s burst sequence and are controlled by the burst address advance(adv ) input. lbo pin is dc operated and determines burst sequence(linear or interleaved). zz pin controls power down state and reduces stand-by cur- rent regardless of clk. the k7b163635b and K7B161835B are fabricated using sam- sung s high performance cmos te chnology and is available in a 100pin tqfp package. multiple power and ground pins are utilized to minimize ground bounce. general description features logic block diagram ? synchronous operation. ? on-chip address counter. ? self-timed write cycle. ? on-chip address and control registers. ? v dd = 2.5 or 3.3v +/- 5% power supply. ? 5v tolerant inputs except i/o pins. ? byte writable function. ? global write enable controls a full bus-width write. ? power down state via zz signal. ? lbo pin allows a choice of either a interleaved burst or a lin- ear burst. ? three chip enables for simple depth expansion with no data contention only for tqfp. ? asynchronous output enable control. ? adsp , adsc , adv burst control pins. ? ttl-level three-state output. ? 100-tqfp-1420a (lead and lead free package) ? operating in commeical and industrial temperature range. clk lbo adv adsc adsp cs 1 cs 2 cs 2 gw bw we x oe zz dqa 0 ~ dqd 7 or dqa0 ~ dqb7 burst control logic burst 512kx36, 1mx18 address control data-in address counter memory array register register logic control register control register a 0 ~a 1 a 0 ~a 1 or a 2 ~a 19 or a 0 ~a 19 dqpa ~ dqpd a 0 ~a 18 a 2 ~a 18 (x=a,b,c,d or a,b) dqpa,dqpb output buffer fast access times parameter symbol -75 unit cycle time t cyc 8.5 ns clock access time t cd 7.5 ns output enable access time t oe 3.5 ns
K7B161835B 512kx36 & 1mx18 synchronous sram - 5 - rev. 3.0 april 2006 k7b163635b pin configuration (top view) pin name notes : 1. a 0 and a 1 are the two least significant bits(lsb) of the address field and set the internal burst counter if burst is desired. symbol pin name tqfp pin no. symbol pin name tqfp pin no. a 0 - a 18 adv adsp adsc clk cs 1 cs 2 cs 2 we x(x=a,b,c,d) oe gw bw zz lbo address inputs burst address advance address status processor address status controller clock chip select chip select chip select byte write inputs output enable global write enable byte write enable power down input burst mode control 32,33,34,35,36,37,42 43,44,45,46,47,48,49 50,81,82,99,100 83 84 85 89 98 97 92 93,94,95,96 86 88 87 64 31 v dd v ss n.c. dqa 0 ~a 7 dqb 0 ~b 7 dqc 0 ~c 7 dqd 0 ~d 7 dqpa~p d or nc v ddq v ssq power supply(+3.3v) ground no connect data inputs/outputs output power supply (2.5v or 3.3v) output ground 15,41,65,91 17,40,67,90 14,16,38,39,66 52,53,56,57,58,59,62,63 68,69,72,73,74,75,78,79 2,3,6,7,8,9,12,13 18,19,22,23,24,25,28,29 51,80,1,30 4,11,20,27,54,61,70,77 5,10,21,26,55,60,71,76 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 pin tqfp (20mm x 14mm) nc/dqpc dqc 0 dqc 1 v ddq v ssq dqc 2 dqc 3 dqc 4 dqc 5 v ssq v ddq dqc 6 dqc 7 n.c. v dd n.c. v ss dqd 0 dqd 1 v ddq v ssq dqd 2 dqd 3 dqd 4 dqd 5 v ssq v ddq dqd 6 dqd 7 nc/dqpd 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 dqpb/nc dqb 7 dqb 6 v ddq v ssq dqb 5 dqb 4 dqb 3 dqb 2 v ssq v ddq dqb 1 dqb 0 v ss n.c. v dd zz dqa 7 dqa 6 v ddq v ssq dqa 5 dqa 4 dqa 3 dqa 2 v ssq v ddq dqa 1 dqa 0 dqpa/nc 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 a 6 a 7 cs 1 cs 2 we d we c we b we a cs 2 v dd v ss clk gw bw oe adsc adsp adv a 8 81 a 9 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 a 15 a 14 a 13 a 12 a 11 a 10 a 17 a 18 v dd v ss n.c. n.c. a 0 a 1 a 2 a 3 a 4 a 5 31 lbo a 16 k7b163635b(512kx36)
K7B161835B 512kx36 & 1mx18 synchronous sram - 6 - rev. 3.0 april 2006 k7b163635b pin configuration (top view) pin name notes : 1. a 0 and a 1 are the two least significant bits(lsb) of the address fi eld and set the internal burst counter if burst is desired. symbol pin name tqfp pin no. symbol pin name tqfp pin no. a 0 - a 19 adv adsp adsc clk cs 1 cs 2 cs 2 we x(x=a,b) oe gw bw zz lbo address inputs burst address advance address status processor address status controller clock chip select chip select chip select byte write inputs output enable global write enable byte write enable power down input burst mode control 32,33,34,35,36,37,42 43,44,45,46,47,48,49 50 80,81,82,99,100 83 84 85 89 98 97 92 93,94 86 88 87 64 31 v dd v ss n.c. dqa 0 ~ a 7 dqb 0 ~ b 7 dqpa, pb v ddq v ssq power supply(+3.3v) ground no connect data inputs/outputs output power supply (2.5v or 3.3v) output ground 15,41,65,91 17,40,67,90 1,2,3,6,7,14,16,25,28,29, 30,38,39,51,52,53,56,57, 66,75,78,79,95,96 58,59,62,63,68,69,72,73 8,9,12,13,18,19,22,23 74,24 4,11,20,27,54,61,70,77 5,10,21,26,55,60,71,76 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 pin tqfp (20mm x 14mm) n.c. n.c. n.c. v ddq v ssq n.c. n.c. dqb 0 dqb 1 v ssq v ddq dqb 2 dqb 3 n.c. v dd n.c. v ss dqb 4 dqb 5 v ddq v ssq dqb 6 dqb 7 dqpb n.c. v ssq v ddq n.c. n.c. n.c. 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 n.c. n.c. v ddq v ssq n.c. dqpa dqa 7 dqa 6 v ssq v ddq dqa 5 dqa 4 v ss n.c. v dd zz dqa 3 dqa 2 v ddq v ssq dqa 1 dqa 0 n.c. n.c. v ssq v ddq n.c. n.c. n.c. 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 a 6 a 7 cs 1 cs 2 n.c. n.c. we b we a cs 2 v dd v ss clk gw bw oe adsc adsp adv a 8 81 a 9 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 a 15 a 14 a 13 a 12 a 11 a 18 a 19 v dd v ss n.c. n.c. a 0 a 1 a 2 a 3 a 4 a 5 31 lbo a 16 K7B161835B(1mx18) a 17 a 10
K7B161835B 512kx36 & 1mx18 synchronous sram - 7 - rev. 3.0 april 2006 k7b163635b function description the k7b163635b and K7B161835B are synchronous sram designed to support the burst address accessing sequence of the power pc based microprocessor. al l inputs (with the exception of oe , lbo and zz) are sampled on rising clock edges. the start and duration of the burst access is controlled by adsc , adsp and adv and chip select pins. the accesses are enabled with the chip select signals and output enabled signals. wait states are in serted into the access wit h adv . when zz is pulled high, the sram will enter a power down state. at this time, internal state of the sram is preserved. when zz returns to low, the sram normally operates after 2cycles of wake up time. zz pin is pulled down internally. read cycles are initiated with adsp (or adsc ) using the new external address clocked into the on-chip address register when both gw and bw are high or when bw is low and we a, we b, we c, and we d are high. when adsp is sampled low, the chip selects are sampled active, and the output buffer is enabled with oe . the data of cell array accessed by t he current address are projected to the output pins. write cycles are also initiated with adsp (or adsc ) and are differentiated into two kinds of operations; all byte write operation and individual byte write operation. all byte write occurs by enabling gw (independent of bw and we x.), and individual byte wr ite is performed only when gw is high and bw is low. in k7b163635b, a 512kx36 organization, we a controls dqa0 ~ dqa7 and dqpa, we b controls dqb0 ~ dqb7 and dqpb, we c controls dqc0 ~ dqc7 and dqpc and we d controls dqd0 ~ dqd7 and dqpd. cs 1 is used to enable the device and conditions internal use of adsp and is sampled only when a new external address is loaded. adv is ignored at the clock edge when adsp is asserted, but can be sampled on the subsequent clock edges. the address increases internally for the next access of the burst when adv is sampled low. addresses are generated for the burst access as shown below, the starting point of the burst seque nce is provided by the extern al address. the burst address counter wraps around to its initial st ate upon completion. the burst sequence is determined by the s tate of the lbo pin. when this pin is low, linear burst sequence is selected. and this pin is high, interleaved burst sequence is selected. burst sequence table (interleaved burst) lbo pin high case 1 case 2 case 3 case 4 a 1 a 0 a 1 a 0 a 1 a 0 a 1 a 0 first address fourth address 0 0 1 1 0 1 0 1 0 0 1 1 1 0 1 0 1 1 0 0 0 1 0 1 1 1 0 0 1 0 1 0 bq table (linear burst) note : 1. lbo pin must be tied to high or low, and floating state must not be allowed . lbo pin low case 1 case 2 case 3 case 4 a 1 a 0 a 1 a 0 a 1 a 0 a 1 a 0 first address fourth address 0 0 1 1 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 0 1 0 1 1 0 0 1 1 0 1 0
K7B161835B 512kx36 & 1mx18 synchronous sram - 8 - rev. 3.0 april 2006 k7b163635b synchronous t ruth table notes : 1. x means "don t care". 2. the rising edge of clock is symbolized by . 3. write = l means write operation in write truth table. write = h means read operation in write truth table. 4. operation finally depends on status of asynchronous input pins(zz and oe ). cs 1 cs 2 cs 2 adsp adsc adv write clk address accessed operation hxxxlx x n/a not selected llxlxxx n/a not selected lxhlxx x n/a not selected llxxlxx n/a not selected lxhxlx x n/a not selected lhllxx x external address begin burst read cycle lhlhlx l external address begin burst write cycle lhlhlx h external address begin burst read cycle xxxhhl h next address continue burst read cycle hxxxhl h next address continue burst read cycle xxxhhl l next address continue burst write cycle hxxxhl l next address continue burst write cycle xxxhhh h current address suspend burst read cycle hxxxhh h current address suspend burst read cycle xxxhhh l current address suspend burst write cycle hxxxhh l current address suspend burst write cycle write truth table ( x36) notes : 1. x means "don t care". 2. all inputs in this table must meet setup and hold time around the rising edge of clk( ). gw bw we a we b we c we d operation hhxxxx read hlhhhh read h l l h h h write byte a h l h l h h write byte b h l h h l l write byte c and d h l l l l l write all bytes lxxxxx write all bytes truth tables write truth table (x18) notes : 1. x means "don t care". 2. all inputs in this table must meet setup and hold time around the rising edge of clk( ). gw bw we a we b operation h h x x read h l h h read h l l h write byte a h l h l write byte b h l l l write all bytes l x x x write all bytes
K7B161835B 512kx36 & 1mx18 synchronous sram - 9 - rev. 3.0 april 2006 k7b163635b asynchronous truth table operation zz oe i/o status sleep mode h x high-z read ll dq l h high-z write l x din, high-z deselected l x high-z notes 1. x means "don t care". 2. zz pin is pulled down internally 3. for write cycles that following read cycles, the output buffers must be disabled with oe , otherwise data bus contention will occur. 4. sleep mode means power down state of which stand-by current does not depend on cycle time. 5. deselected means power down state of which stand-by current depends on cycle time. absolute maximum ratings* *note : stresses greater than those listed under "absolute maximum rati ngs" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at thes e or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating condi tions for extended periods may affect reliability. parameter symbol rating unit voltage on v dd supply relative to v ss v dd -0.3 to 4.6 v voltage on v ddq supply relative to v ss v ddq v dd v voltage on input pin relative to v ss v in -0.3 to v dd +0.3 v voltage on i/o pin relative to v ss v io -0.3 to v ddq +0.3 v power dissipation p d 1.6 w storage temperature t stg -65 to 150 c operating temperature commercial t opr 0 to 70 c industrial t opr -40 to 85 c storage temperature range under bias t bias -10 to 85 c capacitance* (t a =25 c, f=1mhz) *note : sampled not 100% tested. parameter symbol test condition min max unit input capacitance c in v in =0v - 5 pf output capacitance c out v out =0v - 6 pf operating conditions (0 c t a 70 c) notes: 1. the above parameters are also guaranteed at industrial temperature range. 2. it should be v ddq v dd parameter symbol min typ. max unit supply voltage v dd1 2.375 2.5 2.625 v v ddq1 2.375 2.5 2.625 v v dd2 3.135 3.3 3.465 v v ddq2 3.135 3.3 3.465 v ground v ss 000v v ddq v il v ddq +1.0v 20% t cyc (min) v ss v ih v ss -1.0v 20% t cyc (min) undershoot timing overshoot timing v ddq +0.5v v ss -0.5v
K7B161835B 512kx36 & 1mx18 synchronous sram - 10 - rev. 3.0 april 2006 k7b163635b dc electrical characteristics notes : 1. the above parameters are also guaranteed at industrial temperature range. 2. reference ac operating c onditions and characteristics for input and timing. 3. data states are all zero. 4. in case of i/o pins, the max. v ih =v ddq +0.3v parameter symbol test conditions min max unit notes input leakage current(except zz) i il v dd =max ; v in =v ss to v dd -2 +2 a output leakage current i ol output disabled, v out =v ss to v ddq -2 +2 a operating current i cc device selected, i out =0ma, zz v il , cycle time t cyc min -75 - 250 ma 1,2 standby current i sb device deselected, i out =0ma, zz v il , f=max, all inputs 0.2v or v dd -0.2v -75 - 170 ma i sb1 device deselected, i out =0ma, zz 0.2v, f=0, all inputs=fixed (v dd -0.2v or 0.2v) - 150 ma i sb2 device deselected, i out =0ma, zz v dd -0.2v, f=max, all inputs v il or v ih - 130 ma output low voltage(3.3v i/o) v ol i ol =8.0ma - 0.4 v output high voltage(3.3v i/o) v oh i oh =-4.0ma 2.4 - v output low voltage(2.5v i/o) v ol i ol =1.0ma - 0.4 v output high voltage(2.5v i/o) v oh i oh =-1.0ma 2.0 - v input low voltage(3.3v i/o) v il -0.3* 0.8 v input high voltage(3.3v i/o) v ih 2.0 v dd +0.3** v 3 input low voltage(2.5v i/o) v il -0.3* 0.7 v input high voltage(2.5v i/o) v ih 1.7 v dd +0.3** v 3 test conditions * the above parameters are also guaranteed at industrial temperature range. parameter value input pulse level(for 3.3v i/o) 0 to 3.0v input pulse level(for 2.5v i/o) 0 to 2.5v input rise and fall time(measured at 20% to 80% for 3.3/2.5v i/o) 1.0v/ns input and output timing reference levels for 3.3v i/o 1.5v input and output timing reference levels for 2.5v i/o v ddq /2 output load see fig. 1
K7B161835B 512kx36 & 1mx18 synchronous sram - 11 - rev. 3.0 april 2006 k7b163635b ac timing characteristics notes : 1. the above parameters are also guaranteed at industrial temperature range. 2. all address inputs must meet the specified setup and hold times for all rising clock edges whenever adsc and/or adsp is sampled low and cs is sampled low. all other synchronous inputs must meet the spec ified setup and hold times whenever this device is chip selected . 3. both chip se lects must be active whenever adsc or adsp is sampled low in order for the this device to remain enabled. 4. adsc or adsp must not be asserted for at least 2 clock after leaving zz state. parameter symbol -75 unit min max cycle time t cyc 8.5 - ns clock access time t cd -7.5ns output enable to data valid t oe -3.5ns clock high to output low-z t lzc 2.5 - ns output hold from clock high t oh 2.5 - ns output enable low to output low-z t lzoe 0-ns output enable high to output high-z t hzoe -3.5 ns clock high to output high-z t hzc -4.0ns clock high pulse width t ch 2.5 - ns clock low pulse width t cl 2.5 - ns address setup to clock high t as 2.0 - ns address status setup to clock high t ss 2.0 -ns data setup to clock high t ds 2.0 -ns write setup to clock high (gw , bw , we x )t ws 2.0 -ns address advance setup to clock high t advs 2.0 -ns chip select setup to clock high t css 2.0 -ns address hold from clock high t ah 0.5 - ns address status hold from clock high t sh 0.5 - ns data hold from clock high t dh 0.5 - ns write hold from clock high (gw , bw , we x )t wh 0.5 - ns address advance hold from clock high t advh 0.5 - ns chip select hold from clock high t csh 0.5 - ns zz high to power down t pds 2 - cycle zz low to power up t pus 2 - cycle output load(b), (for t lzc , t lzoe , t hzoe & t hzc ) dout 353 ? / 1538 ? 5pf* +3.3v for 3.3v i/o 319 ? / 1667 ? fig. 1 * including scope and jig capacitance output load(a) dout zo=50 ? rl=50 ? vl=1.5v for 3.3v i/o v ddq /2 for 2.5v i/o /+2.5v for 2.5v i/o
K7B161835B 512kx36 & 1mx18 synchronous sram - 12 - rev. 3.0 april 2006 k7b163635b clock adsp adsc address write cs adv oe data out timing waveform of read cycle notes : write = l means gw = l, or gw = h, bw = l, we x.= l cs = l means cs 1 = l, cs 2 = h and cs 2 = l cs = h means cs 1 = h, or cs 1 = l and cs 2 = h, or cs 1 = l, and cs 2 = l t ch t cl t ss t sh t ss t sh t as t ah a1 a2 a3 burst continued with new base address t ws t wh t css t csh t advs t advh t oe t hzoe t lzoe t cd t oh (adv inserts wait state) t hzc q3-4 q3-3 q3-2 q3-1 q2-4 q2-3 q2-2 q2-1 q1-1 don t care undefined t cyc
K7B161835B 512kx36 & 1mx18 synchronous sram - 13 - rev. 3.0 april 2006 k7b163635b clock adsp adsc address write cs adv data in oe data out t ch t cl t ss t sh t as t ah a1 a2 a3 (adsc extended burst) t lzoe d2-1 d1-1 t css t csh (adv suspends burst) d2-2 d2-3 d2-4 d3-1 d3-2 d3-3 d2-2 d3-4 q0-3 q0-4 t ss t sh t ws t wh t advs t advh t ds t dh timing waveform of wrte cycle don t care undefined t cyc
K7B161835B 512kx36 & 1mx18 synchronous sram - 14 - rev. 3.0 april 2006 k7b163635b timing waveform of combination read/wrte cycle(adsp controlled, adsc =high) clock adsp address write cs adv oe data out t ch t cl t ds t dh q3-3 data in t oe t oh a1 a2 a3 d2-1 q3-1 q3-2 q3-4 t ss t sh t as t ah t ws t wh t advs t advh t lzoe t hzoe t cd t hzc t lzc don t care undefined t cyc q1-1
K7B161835B 512kx36 & 1mx18 synchronous sram - 15 - rev. 3.0 april 2006 k7b163635b timing waveform of single read/write cycle(adsc controlled, adsp =high) clock adsc address write cs adv oe data in t ch t cl t hzoe d6-1 data out t ws t wh t cd t oh t oe d5-1 d7-1 t ws t wh t lzoe t dh t ds a1 a2 a3 a4 a5 a6 a7 a8 a9 q3-1 q1-1 q2-1 q4-1 q8-1 q9-1 t css t csh t ss t sh don t care undefined t cyc
K7B161835B 512kx36 & 1mx18 synchronous sram - 16 - rev. 3.0 april 2006 k7b163635b d7-1 timing waveform of single read/write cycle(adsp controlled, adsc =high) clock adsp address write cs adv oe data in t ch t cl t hzoe data out t as t ah t cd t oh t oe d5-1 t lzoe t dh t ds a1 a2 a3 a4 a5 a6 a9 q3-1 q1-1 q2-1 q4-1 q8-1 q9-1 t css t csh t ss t sh a7 a8 d6-1 don t care undefined t cyc
K7B161835B 512kx36 & 1mx18 synchronous sram - 17 - rev. 3.0 april 2006 k7b163635b timing waveform of power down cycle clock adsp address write cs adv data in t ch t cl d2-2 oe t wh t hzoe t lzoe d2-1 a1 t ss t sh data out t pus a2 adsc q1-1 zz t as t ah t css t csh t oe t hzc t pds sleep state zz setup cycle normal operation mode zz recovery cycle t ws don t care undefined t cyc
K7B161835B 512kx36 & 1mx18 synchronous sram - 18 - rev. 3.0 april 2006 k7b163635b application information depth expansion data address clk ads cs 2 cs 2 clk adsc we x oe cs 1 address data adv adsp 512kx36 sb sram (bank 0) cs 2 cs 2 clk adsc we x oe cs 1 address data adv adsp 512kx36 sb sram (bank 1) clk address cache controller a [0:19] a [19] a [0:18] a [19] a [0:18] i/o [0:71] microprocessor *notes : n = 14 32k depth , 15 64k depth 16 128k depth , 17 256k depth 18 512k depth , 19 1m depth clock adsp address data out interleave read timing (refer to non-interleave write timing for interleave write timing) bank 0 is selected by cs 2 , and bank 1 deselected by cs 2 q1-1 q1-2 q1-4 q1-3 oe data out t ss t sh a1 a2 write cs 1 a n+1 adv (bank 0) (bank 1) q2-1 q2-2 q2-4 q2-3 t as t ah t css t csh t ws t wh t advs t advh t oe t lzoe t hzc bank 0 is deselected by cs 2 , and bank 1 selected by cs 2 [0:n] don t care undefined t cd t lzc the samsung 512kx36 synchronous burst sram has two addi tional chip selects for simple depth expansion. this permits easy secondary cache upgrades from 512k depth to 1m depth without extra logic. (adsp controlled , adsc =high)
K7B161835B 512kx36 & 1mx18 synchronous sram - 19 - rev. 3.0 april 2006 k7b163635b application information the samsung 1mx18 synchronous burst sram has two addi tional chip selects for simple depth expansion. depth expansion this permits easy secondary cache upgrades from 1m depth to 2m depth without extra logic. data address clk ads microprocessor cs 2 cs 2 clk adsc we x oe cs 1 address data adv adsp 1mx18 sb sram (bank 0) cs 2 cs 2 clk adsc we x oe cs 1 address data adv adsp 1mx18 sb sram (bank 1) clk address cache controller a [0:20] a [20] a [0:19] a [20] a [0:19] i/o [0:71] clock adsp address data out interleave read timing (refer to non-interleave write timing for interleave write timing) bank 0 is selected by cs 2 , and bank 1 deselected by cs 2 q1-1 q1-2 q1-4 q1-3 oe data out t ss t sh a1 a2 write cs 1 a n+1 adv (bank 0) (bank 1) q2-1 q2-2 q2-4 q2-3 t as t ah t css t csh t ws t wh t advs t advh t oe t lzoe t hzc bank 0 is deselected by cs 2 , and bank 1 selected by cs 2 [0:n] don t care undefined t cd t lzc (adsp controlled , adsc =high) *notes : n = 14 32k depth , 15 64k depth 16 128k depth , 17 256k depth 18 512k depth , 19 1m depth 20 2m depth
K7B161835B 512kx36 & 1mx18 synchronous sram - 20 - rev. 3.0 april 2006 k7b163635b package dimensions 0.10 max 0~8 22.00 0.30 20.00 0.20 16.00 0.30 14.00 0.20 1.40 0.10 1.60 max 0.05 min (0.58) 0.50 0.10 #1 (0.83) 0.50 0.10 100-tqfp-1420a (lead and lead free package) 0.65 0.30 0.10 0.10 max + 0.10 - 0.05 0.127 units ; millimeters/inches

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